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HI5780
August 1997
10-Bit, 80 MSPS, High Speed, Low Power D/A Converter
Description
The HI5780 is a 10-bit, 80 MSPS, high speed, low power CMOS D/A converter. The converter incorporates a 10-bit input data register with current outputs. The HI5780 includes a power down feature that reduces power consumption and a blanking control. The on-chip bandgap reference can be used to set the output current range of the D/A.
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Features
* Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 80 MSPS * Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150mW * Differential Linearity Error . . . . . . . . . . . . . . . 0.5 LSB * TTL/CMOS Compatible Inputs * Built in Bandgap Voltage Reference * Power Down and Blanking Control Pins * Direct Replacement for Sony CXD2306
Ordering Information
PART NUMBER HI5780JCQ HI5780-EV TEMP. RANGE (oC) -20 to 75 25 PACKAGE 32 Ld MQFP Evaluation Kit PKG. NO. Q32.7x7-S
Applications
* Wireless Communications * Direct Digital Frequency Synthesis * Signal Reconstruction * Test Equipment * High Resolution Imaging and Graphics Systems * Arbitrary Waveform Generators
Pinout
HI5780 (MQFP)
D0 (LSB)
DGND
D3 D4 D5 D6 D7 D8 D9 (MSB) NC
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
AGND
DVDD
NC
NC
D2
D1
IOUT IOUT VG AVDD AVDD VREF REFOUT IREF
PD
VB
DGND
CLK
BLK
NC
DVDD
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4024.4
10-1716
HI5780 Typical Application Circuit
+5V 0.01F DVDD (13, 28) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 (MSB) (7) D8 (6) D7 (5) D6 (4) D5 (3) D4 (2) D3 (1) D2 (32) D1 (31) D0 (30) CLK (9) 50 BLK (10) DGND (8, 12,15, 16, 26, 27, 29) POWER DOWN CONTROL PD (11) (25) AGND (17) IREF 2.0k (23) IOUT (24) IOUT 200 D/A OUT (14) VB (18) REFOUT (19) VREF 0.1F (20, 21) AVDD 0.1F (22) VG +5V HI5780 0.01F
Functional Block Diagram
(LSB) D0 D1 D2 D3 4 LSB CURRENT CELLS
IOUT
D4 D5 D6 D7 D8 (MSB) D9 DECODER DECODER
DATA REGISTER 6 MSB CURRENT CELLS
IOUT
VG
BLK CLOCK GENERATOR
CURRENT CELLS (FOR FULL SCALE)
+
-
VREF IREF
CLK
BIAS VOLTAGE GENERATOR
VB PD
BANDGAP VOLTAGE REFERENCE
REFOUT
10-1717
HI5780
Absolute Maximum Ratings
Supply Voltage VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Digital Input Voltages (D9-D0, CLK, BLANK, PD) . . . . VDD to -0.5V Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . 2.5mA Reference Input Voltage Range (VREF) . . . . . . . . . . . . VDD to -0.5 V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only)
Operating Conditions
Temperature Range, HI5780BIx . . . . . . . . . . . . . . . . . -20oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD , DVDD = 5.00V, VREF = 2.0V, fCLK = 80 MSPS, RLOAD = 200, RREF = 3.3k, TA = 25oC HI5780JCQ
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Full Scale Output Current, IFS Full Scale Drift Coefficient, IDRIFT Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Throughput Rate Output Voltage Full Scale Step Settling Time, tSETT FS Singlet Glitch Area, GE (Peak) Differential Gain, DG Differential Phase, DP Spurious Free Dynamic Range, SFDR to Nyquist (Note 3)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10 (Notes 4, 5) ("Best Fit" Straight Line) (Notes 4, 5) (Notes 4, 5) (Note 4) (Note 2) (Note 3), 10-Bit Accuracy -2.0 -0.5 9.0 1.8
1.25 0.25 9.6 0.26 1.92
2.0 0.5 5 10 2.0
Bits LSB LSB A mA mV/oC V
80.0 -
6.0 40 2.5 1.3 48.5 47.5 40.75 38.5 75.0 73.5 56.5 49.0
-
MSPS ns pV-s % Degrees dBc dBc dBc dBc dBc dBc dBc dBc
To 0.5 LSB Error Band RL = 75, 10-Bit Accuracy (Note 3) RLOAD = 75, VOUT = 1.0VP-P (Note 3) (Note 4) (Note 4) fCLK = 40 MSPS, fOUT = 2.02MHz, 20MHz Span (Note 3) fCLK = 80 MSPS, fOUT = 2.02MHz, 40MHz Span (Note 3) fCLK = 40 MSPS, fOUT = 10MHz, 20MHz Span (Note 3) fCLK = 80 MSPS, fOUT = 20MHz, 40MHz Span (Note 3)
Spurious Free Dynamic Range, SFDR Within a Window
fCLK = 40 MSPS, fOUT = 2.02MHz, 2MHz Span (Note 3) fCLK = 80 MSPS, fOUT = 2.02MHz, 2MHz Span (Note 3) fCLK = 40 MSPS, fOUT = 10MHz, 2MHz Span (Note 3) fCLK = 80 MSPS, fOUT = 20MHz, 2MHz Span (Note 3)
REFERENCE Internal Reference Voltage, REFOUT Internal Reference Voltage Drift Reference Input Voltage Range, VREF (Notes 4, 5) (Note 3) (Note 3) 1.0 0.5 1.25 0.34 1.3 2.0 V mV/oC V
10-1718
HI5780
Electrical Specifications
AVDD , DVDD = 5.00V, VREF = 2.0V, fCLK = 80 MSPS, RLOAD = 200, RREF = 3.3k, TA = 25oC (Continued) HI5780JCQ PARAMETER DIGITAL INPUTS (D9-D0, CLK, BLK, PD) Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLK Pulse Width, tPW1 , tPW2 POWER SUPPLY CHARACTERISTICS IVDD Power Dissipation Sleep Mode Power Consumption NOTES: 2. RLOAD is connected to IOUT (pin 24) and RREF is connected to IREF (pin 17). 3. Parameter guaranteed by design or characterization and not production tested. 4. Typical values are test results at TA = 25oC. 5. All devices are 100% tested at 25oC. (Notes 4, 5) (Note 5) PD = 1 (Note 4) 20 100 1.25 30 150 mA mW mW (See Figure 1, Note 3) (See Figure 1, Note 3) (See Figure 1, Note 3) (See Figure 1, Note 3) 5.0 1.0 6.25 3.0 0 8.0 ns ns ns ns (Note 5) (Note 5) (Note 5) (Note 5) (Note 3) 2.15 -5 3.0 0.85 5 V V A A pF TEST CONDITIONS MIN TYP MAX UNITS
Timing Diagrams
CLK
50%
D9-D0
1/
2
LSB ERROR BAND
V
GLITCH AREA = 1/2 (H x W)
IOUT
HEIGHT (H)
tPD
tSETT
WIDTH (W)
t(ps)
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD
10-1719
HI5780 Timing Diagrams (Continued)
tPW1 tPW2
CLK
50%
tSU tHLD D9-D0
tSU tHLD
tSU tHLD
tPD
tSETT
1
/2 LSB CHANGE
IOUT
1/ 2 LSB CHANGE
tPD
tSETT
tPD
tSETT
FIGURE 3. PROPAGATION DELAY, SETUP TIME AND MINIMUM PULSE WIDTH DIAGRAM
Pin Descriptions
PIN 1-7, 30-32 PIN NAME D0 (LSB) thru D9 (MSB) CLK DVDD DGND AVDD BLK AGND PD DESCRIPTION Digital Data Bit 0, the least significant bit thru digital data Bit 9, the most significant bit.
9 13, 28 15, 27 20, 21 23 25 11
Data Clock Pin 100kHz to 80MHz. Digital Logic Supply +5V. Digital Ground. Analog Supply +5V. Output Blanking pin. When set (`1') this pin zeros the IOUT pin. Analog Ground Supply Current Return pin. Power Down Mode pin. This pin when set (`1') places the HI5780 in lower power mode and zeros the output. Power consumption is reduced. Current Output pin. Complementary Current Output pin. Bandgap Reference Voltage Output. Reference Current setting resistor connected from here to Ground. Reference Voltage Input pin. Bias Voltage Generator Bypass Capacitor connected from here to Ground. Reference Amplifier Bypass Capacitor connected from here to AVDD .
24 23 18 17 19 14 22
IOUT IOUT REFOUT IREF VREF VB VG
10-1720
HI5780 Typical Performance Curves
1.0 0.75 0.5 0.25 LSB LSB 0 100 200 300 400 500 CODE 600 700 800 900 1000 0 -0.25 -0.5 -0.75 -1.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 100 200 300 400 500 CODE 600 700 800 900 1000
FIGURE 4. DIFFERENTIAL LINEARITY
FIGURE 5. INTEGRAL LINEARITY (BEST FIT - STRAIGHT LINE)
23 -10 22 21 20 mA 19 18 17 16 15 10 20 30 40 50 60 MHz 70 80 90 100 -20 -30 -40 S -50 -60 -70 -80 -90 -100
ATTEN 10dB RL -10.0dBm
10dB/
MKR -48.50dB 2.00MHz HI5780 fS = 40 MSPS fO = 2MHz
START 0Hz RBW 1.0kHz
VBW 1.0kHz
STOP 20.00MHz SWP 50.0s
FIGURE 6. POWER SUPPLY CURRENT vs CLOCK FREQUENCY
FIGURE 7. SPURIOUS FREE DYNAMIC RANGE TO NYQUIST
ATTEN 10dB RL -10.0dBm
10dB/ HI5780 fS = 40 MSPS fO = 2MHz
MKR -75.00dB 33kHz
S
CENTER 2.000MHz RBW 300Hz
VBW 300Hz
SPAN 2.000MHz SWP 56.0s
FIGURE 8. SPURIOUS FREE DYNAMIC RANGE WITHIN A WINDOW
10-1721
HI5780 Detailed Description
The HI5780 is a 10-bit, current out D/A converter. The DAC can convert at 80 MSPS and runs on +5V supplies. The HI5780 achieves its low power and high speed performance from an advanced CMOS process. The HI5780 consumes 150mW (Maximum) and has a power down mode that only consumes 1.25mW when in sleep mode. The HI5780 is an excellent converter to be used for communications applications and high performance video systems. Digital Inputs The HI5780 is a TTL/CMOS-compatible D/A. Data is latched by a 10-bit latch. Once latched data inputs D0 (LSB) thru D9 (MSB) are decoded to the internal current cells; the internal latch and switching current source controls are implemented in CMOS technology to maintain high switching speeds and low power consumption. Clocks and Termination The internal 10-bit register is updated on the rising edge of the clock. Since the HI5780 clock rate can run to 80MHz, to minimize reflections and clock noise into the part, proper termination should be used. In PCB layout clock runs should be kept short and have a minimum of loads. To guarantee consistent results from board to board, controlled impedance PCBs should be used with a characteristic line impedance, ZO , of 50 . To terminate the clock line a shunt terminator to ground is the most effective type at a 80 MSPS clock rate. A typical value for termination can be determined by the equation:
RT = Z O ,
Reference The internal reference in the HI5780 is a 1.25V (typical) bandgap voltage reference. The internal reference is buffered by an amplifier to provide adequate drive for the current cells. Reference Out (REFOUT) is connected to the VREF pin. The Full Scale Output Current is controlled by the resistor connected to IREF . The full scale output voltage, is set by the following equation:
VO UT (Full Scale) = V REF x 16 ( R LOAD /R REF ).
Applications
Voltage Conversion of the Output To convert the output current of the D/A converter to a voltage, an amplifier should be used as shown in Figure 5. The DAC needs a 50 termination resistor on the IOUT pin to ensure proper settling. The HFA1110 has an internal feedback resistor to compensate for high frequency operation.
+5V 2 HI5780 DAC IOUT 21 50 4 + 1
HFA1110 8
6
5 -5.2V
50
FIGURE 10. HIGH SPEED CURRENT TO VOLTAGE CONVERSION
for the termination resistor. For a controlled impedance board with a ZO of 50, the RT = 50. Shunt termination is best used at the receiving end of the transmission line or as close to the HI5780 CLK pin as possible.
HI5780 DAC ZO = 50 CLK RT = 50
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Output Voltage Full Scale Settling Time, is the time required from the 50% point on the clock input for a full scale step to settle within an 1/2 LSB error band. Glitch Area, GE, is the switching transient appearing on the output during a code transition. It is measured as the area under the curve and expressed as a Volt-Time specification. Differential Gain, AV , is the gain error from an ideal sine wave with a normalized amplitude. Differential Phase, , is the phase error from and ideal sine wave. Spurious Free Dynamic Range, SFDR, is the amplitude difference from a fundamental to the largest harmonically or non-harmonically related spur. A sine wave is loaded into the D/A and the output filtered at 1/2 the clock frequency to eliminate noise from clocking alias terms.
FIGURE 9. AC TERMINATION OF THE HI5780 CLOCK LINE
Rise and Fall times and propagation delay of the line will be affected by the Shunt Terminator. The terminator can be connected to DGND. Noise Reduction To reduce power supply noise, separate analog and digital power supplies should be used with 0.1F and 0.01F ceramic capacitors placed as close to the body of the HI5780 as possible on the analog (AVDD) and digital (DVDD) supplies. The analog and digital ground returns should be connected together back at the device to ensure proper operation on power up.
10-1722
HI5780
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
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Spec Number 10-1723

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